`timescale 1ps/1ps
//***************************************************************************
//   Copyright(c)2020, Xidian University D405.
//           All rights reserved
//
//   File name       :   axi_read_channel_txfifo.v
//   Module name     :   axi_read_channel_txfifo
//   Author          :   Zhao Yuchen
//   Date            :   2022/04/07
//   Version         :   v3.00
//   Edited by       :   Zhao Yuchen,wzk 0419 distinguish 10g/40g parameter
//***************************************************************************
//`define VCS_MODEL
module axi_read_channel_txfifo #
(
    parameter MAC_DWIDTH = 64  , // MAC Data Width
    parameter MAC_KWIDTH = 8   , // MAC Keep Width
    parameter MAC_KBITS  = 3   , // MAC Keep Bits
    parameter MAC_UWIDTH = 4   , // MAC User Width
    parameter DMA_DWIDTH = 128 , // DMA Data Width
    parameter LEN_DWIDTH = 11  , // LEN Data Width
    parameter MEM_AWIDTH_10g = 10  , // MEM Addr Width
    parameter LEN_AWIDTH_10g = 10  , // LEN Addr Width
    parameter MEM_AWIDTH_40g = 10  , // MEM Addr Width
    parameter LEN_AWIDTH_40g = 10    // LEN Addr Width
)
(
    //********** 10G **********//
    input  wire  wclk_10g,
    input  wire  rclk_10g,
	input  wire  rstn_wclk_10g,
	input  wire  rstn_rclk_10g,
    
    input  wire  start_i_10g,
    //Write
    input  wire                    wr_data_en_i_10g    ,
    input  wire                    wr_leng_en_i_10g    ,
    input  wire [DMA_DWIDTH-1 : 0] wr_data_i_10g       ,
    input  wire [LEN_DWIDTH-1 : 0] wr_leng_i_10g       ,
    output wire                    wr_full_o_10g       ,
    
    
    output wire                    m_axis_tvalid_o_10g ,
    output wire                    m_axis_tlast_o_10g  ,
    output wire [MAC_KWIDTH-1 : 0] m_axis_tkeep_o_10g  ,
    output wire [MAC_DWIDTH-1 : 0] m_axis_tdata_o_10g  ,
    input                          m_axis_tready_i_10g ,
    output wire [MAC_UWIDTH-1 : 0] m_axis_tuser_o_10g  ,
	
	//********** 40G **********//
    input  wire  wclk_40g,
    input  wire  rclk_40g,
	input  wire  rstn_wclk_40g,
	input  wire  rstn_rclk_40g,
    
    input  wire  start_i_40g,
    //Write
    input  wire                    wr_data_en_i_40g    ,
    input  wire                    wr_leng_en_i_40g    ,
    input  wire [DMA_DWIDTH-1 : 0] wr_data_i_40g       ,
    input  wire [LEN_DWIDTH-1 : 0] wr_leng_i_40g       ,
    output wire                    wr_full_o_40g       ,
    
    
    output wire                    m_axis_tvalid_o_40g ,
    output wire                    m_axis_tlast_o_40g  ,
    output wire [MAC_KWIDTH-1 : 0] m_axis_tkeep_o_40g  ,
    output wire [MAC_DWIDTH-1 : 0] m_axis_tdata_o_40g  ,
    input                          m_axis_tready_i_40g ,
    output wire [MAC_UWIDTH-1 : 0] m_axis_tuser_o_40g  ,
    input  wire [11:0]             ram_dp_cfg_register
);

txfifo2axis_10g #
(
	.MAC_DWIDTH                 (MAC_DWIDTH),  
	.MAC_KWIDTH                 (MAC_KWIDTH),
	.MAC_KBITS                  (MAC_KBITS ),
	.MAC_UWIDTH                 (MAC_UWIDTH),
	.DMA_DWIDTH                 (DMA_DWIDTH),
	.LEN_DWIDTH                 (LEN_DWIDTH),
	.MEM_AWIDTH                 (MEM_AWIDTH_10g),
	.LEN_AWIDTH                 (LEN_AWIDTH_10g)
)
txfifo2axis_10g
(
	.wclk                       (wclk_10g),                    
	.rclk                       (rclk_10g),                    
    .rstn_rclk                  (rstn_rclk_10g),
    .rstn_wclk                  (rstn_wclk_10g), 					   
	.start_i                    (start_i_10g),  
	.wr_data_en_i               (wr_data_en_i_10g),          
	.wr_leng_en_i               (wr_leng_en_i_10g),          
	.wr_data_i                  (wr_data_i_10g),            
	.wr_leng_i                  (wr_leng_i_10g),            
	.wr_full_o                  (wr_full_o_10g),                
	//AXI-Stream OUTPUT to MAC                             
	.m_axis_tvalid_o            (m_axis_tvalid_o_10g),     
	.m_axis_tlast_o             (m_axis_tlast_o_10g),      
	.m_axis_tkeep_o             (m_axis_tkeep_o_10g),      
	.m_axis_tdata_o             (m_axis_tdata_o_10g),      
	.m_axis_tready_i            (m_axis_tready_i_10g),     
	.m_axis_tuser_o             (m_axis_tuser_o_10g),
  .ram_dp_cfg_register    		(ram_dp_cfg_register)
);

txfifo2axis_40g #
(
	.MAC_DWIDTH                 (MAC_DWIDTH),  
	.MAC_KWIDTH                 (MAC_KWIDTH),
	.MAC_KBITS                  (MAC_KBITS ),
	.MAC_UWIDTH                 (MAC_UWIDTH),
	.DMA_DWIDTH                 (DMA_DWIDTH),
	.LEN_DWIDTH                 (LEN_DWIDTH),
	.MEM_AWIDTH                 (MEM_AWIDTH_40g),
	.LEN_AWIDTH                 (LEN_AWIDTH_40g)
)
txfifo2axis_40g
(
	.wclk                       (wclk_40g),                    
	.rclk                       (rclk_40g),                    
    .rstn_rclk                  (rstn_rclk_40g),
    .rstn_wclk                  (rstn_wclk_40g),			   
	.start_i                    (start_i_40g),  
	.wr_data_en_i               (wr_data_en_i_40g),          
	.wr_leng_en_i               (wr_leng_en_i_40g),          
	.wr_data_i                  (wr_data_i_40g),            
	.wr_leng_i                  (wr_leng_i_40g),            
	.wr_full_o                  (wr_full_o_40g),                
	//AXI-Stream OUTPUT to MAC                             
	.m_axis_tvalid_o            (m_axis_tvalid_o_40g),     
	.m_axis_tlast_o             (m_axis_tlast_o_40g),      
	.m_axis_tkeep_o             (m_axis_tkeep_o_40g),      
	.m_axis_tdata_o             (m_axis_tdata_o_40g),      
	.m_axis_tready_i            (m_axis_tready_i_40g),     
	.m_axis_tuser_o             (m_axis_tuser_o_40g),
  .ram_dp_cfg_register    		(ram_dp_cfg_register)
);

endmodule
